In an active matrix liquid crystal display, each pixel has a thin film transistor (TFT). The gate electrode of the TFT is electrically connected to a scanning line in the horizontal direction, the drain electrode is electrically connected to a data line in the vertical direction, and the source electrode is electrically connected to a pixel electrode. If a sufficient positive voltage is applied to a certain scanning line in the horizontal direction, all TFTs on this scanning line will be turned on. The pixel electrode corresponding to this scanning line is connected with the data line in the vertical direction, and the signal voltage on the data line is written into the pixel. Generally, the driving circuit is mainly constituted by an integrated circuit (IC) adhered outside the liquid crystal panel.
In recent years, the GOA technology is proposed. The GOA technology manufactures the gate driver circuit on an array substrate directly, so as to replace the driving chip manufactured by an external silicon wafer. Nowadays, in the field of liquid crystal display technology, the GOA technology has been developed and applied widely, because the GOA technology can reduce the production process and reduce the product process cost. In addition, the GOA panel can be classified into a unilateral GOA panel and a bilateral GOA panel in terms of the GOA distribution.
Although the GOA technology has been widely used in the liquid crystal manufacturing field, due to the complexity of its circuit connection and process, the yield rate of the GOA circuit is not very high. One of the main factors that influence its yield rate is electro-static accumulation and electro-static discharge (ESD). In the existing manufacturing process of the GOA circuit, because the wires on the panel are relatively close to each other, the unfavorable conditions such as ESD may occur easily.
FIG. 1 is a schematic diagram representing a display panel using the GOA technology in the prior art.
As shown in FIG. 1, in the display panel using the GOA technology, the display panel includes: a display area and a GOA area. The display area includes a plurality of gate lines and a plurality of data lines that intersect with each other vertically and horizontally. GOA units are arranged in the GOA area. If ESD and short (i.e., the short circuit point in FIG. 1) occur, for the display panel using the GOA technology, at present, they can only be investigated one by one along the wires of the panel (gate lines and data lines) and the GOA units, and it is not ensured to find them. Because the ESD points within the GOA unit and between the signal wires are elusive, it is not easy to be found and positioned accurately, which influences the analysis and improvement. Hence, in such a situation, the analysis efficiency of the ESD related defects will be reduced and the improving accuracy thereof will also be reduced.